Currently, an eFUSE element disclosed in Non-patent Document 1 described below and an insulating film breakdown type element disclosed in Patent Document 1 have been known as a memory element that can be used as a ROM (Read Only Memory).
The memory element disclosed in Non-patent Document 1 is configured as a resistance element having a stacked structure of a polysilicon/silicide/silicon nitride film that is the same as a wiring structure employed in a normal logic LSI process, with two terminals which are a cathode and an anode. A large current is flown through the resistance element for heating, an atom of a material for a metal wire is migrated or melted in a direction of an electron flow to cause breakdown, and then a resistance value between two terminals is changed. In addition, there is an example in which a resistance value is changed by externally entering a laser beam, instead of flowing a large current, to break down a wire.
The memory element (anti-fuse) disclosed in Patent Document 1 has a MOS transistor structure. It performs writing by causing dielectric breakdown that is generated by an application of high electric field to a gate insulating film
As another example, an element utilizing a property of a variable resistance element is disclosed in Patent Documents 2 and 3. The element disclosed in Patent Document 2 is a transistor element including first and second conductive layer patterns (corresponding to a source electrode and a drain electrode) spaced apart on an insulating film, a physical property transformation layer formed on the insulating film between the conductive layer patterns, a high dielectric film (corresponding to a gate insulating film) stacked onto the physical property transformation layer, and a gate electrode formed on the high dielectric film. When a voltage between the source and drain exceeds a first threshold voltage in the case where an applied voltage to the gate electrode is 0 V, the resistance of the physical property transformation layer is reduced, whereby the element is set to a conducting state. On the other hand, when a predetermined voltage higher than 0 V is applied to the gate electrode, a channel is formed below the physical property transformation layer. Therefore, when the voltage between the source and drain exceeds a second threshold voltage that is lower than the first threshold voltage, the element is set to a conducting state. Accordingly, the element can be used as a switching element that switches the conducting state and a non-conducting state depending upon the application state of the gate voltage by setting the voltage between the source and drain to the voltage between the first threshold voltage and the second threshold voltage.
The element disclosed in Patent Document 3 is a 3-terminal variable resistance element including first and second electrodes (corresponding to a source electrode and a drain electrode), a variable resistance body electrically connected to both of the first and second electrodes, and a control electrode that is opposite to the variable resistance body via a dielectric layer (corresponding to a gate insulating film). When a reading voltage is applied between the first and second electrodes with a voltage being applied to the control electrode, a resistance property between the first and second electrodes shows temporarily reduced resistance, whereby a large reading current can be obtained by a low reading voltage, and a reading margin can be set large.